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74F240 * 74F241 * 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs
April 1988 Revised January 2004
74F240 * 74F241 * 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs
General Description
The 74F240, 74F241 and 74F244 are octal buffers and line drivers designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC and board density.
Features
s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs sink 64 mA (48 mA mil) s 12 mA source current s Input clamp diodes limit high-speed termination effects
Ordering Code:
Order Code 74F240SC (Note 1) 74F240SJ (Note 1) 74F240PC 74F241SC 74F241PC 74F244SC (Note 1) 74F244SJ (Note 1) 74F244MSA (Note 1) 74F244PC Package Number M20B M20D N20A M20B N20A M20B M20D MSA20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
74F240 74F241
74F244
(c) 2004 Fairchild Semiconductor Corporation
DS009501
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74F240 * 74F241 * 74F244
Logic Symbols
IEEE/IEC 74F240 IEEE/IEC 74F241
IEEE/IEC 74F244
Unit Loading/Fan Out
Pin Names OE1, OE2 OE2 I0-I7 I0-I7 Description 3-STATE Output Enable Input (Active LOW) 3-STATE Output Enable Input (Active HIGH) Inputs (74F240) Inputs (74F241, 74F244) U.L. HIGH/LOW 1.0/1.667 1.0/1.667 1.0/1.667 (Note 2) 1.0/2.667 (Note 2) 600/106.6 (80) Input IIH/IIL Output IOH/IOL 20 A/-1 mA 20 A/-1 mA 20 A/-1 mA 20 A/-1.6 mA
O0-O7, O0-O7 Outputs
Note 2: Worst-case 74F240 enabled; 74F241, 74F244 disabled
-12 mA/64 mA (48 mA)
Truth Tables
74F240 OE1 H L L D1n X H L O1n Z L H 74F241 OE1 H L L D1n X H L O1n Z H L OE2 L H H D2n X H L O2n Z H L OE2 H L L D2n X H L O2n Z L H OE1 H L L D1n X H L 74F244 O1n Z H L OE2 H L L D2n X H L O2n Z H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
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74F240 * 74F241 * 74F244
Absolute Maximum Ratings(Note 3)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 4) Input Current (Note 4) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage VOL IIH IBVI ICEX VID IOD Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current IIL IOZH IOZL IOS IZZ ICCH ICCL ICCZ ICCH ICCL ICCZ Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current (74F240) Power Supply Current (74F240) Power Supply Current (74F240) Power Supply Current (74F241, 74F244) Power Supply Current (74F241, 74F244) Power Supply Current (74F241, 74F244) 19 50 42 40 60 60 -100 4.75 3.75 -1.0 -1.6 50 -50 -225 500 29 75 63 60 90 90 10% VCC 10% VCC 5% VCC 10% VCC 2.4 2.0 2.7 0.55 5.0 7.0 50 V A A A V A Min Max Max Max 0.0 0.0 V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -3 mA IOH = -15 mA IOH = -3 mA IOL = 64 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (OE1, OE2, OE2, Dn 74F240)) VIN = 0.5V (Dn (74F241, 74F244)) VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH VO = LOW VO = HIGH Z VO = HIGH VO = LOW VO = HIGH Z
mA A A mA A mA mA mA mA mA mA
Max Max Max Max 0.0V Max Max Max Max Max Max
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74F240 * 74F241 * 74F244
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Output (74F241, 74F244) Output Enable Time (74F241, 74F244) Output Disable Time (74F241, 74F244) Output Disable Time (74F240) Propagation Delay Data to Output (74F240) Output Enable Time (74F240) 3.0 2.0 2.0 4.0 2.0 2.0 2.5 2.5 2.0 2.0 2.0 2.0 VCC = +5.0V CL = 50 pF Typ 5.1 3.5 3.5 6.9 4.0 6.0 4.0 4.0 4.3 5.4 4.5 4.5 Max 7.0 4.7 4.7 9.0 5.3 8.0 5.2 5.2 5.7 7.0 6.0 6.0 TA = -55C to +125C VCC = 5.0V CL = 50 pF Min 3.0 2.0 2.0 4.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 9.0 6.0 6.5 10.5 6.5 12.5 6.5 7.0 7.0 8.5 7.0 7.5 TA = 0C to +70C VCC = 5.0V CL = 50 pF Min 3.0 2.0 2.0 4.0 2.0 2.0 2.5 2.5 2.0 2.0 2.0 2.0 Max 8.0 5.7 5.7 10.0 6.3 9.5 6.2 6.5 6.7 8.0 7.0 7.0 ns ns ns ns Units
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74F240 * 74F241 * 74F244
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74F240 * 74F241 * 74F244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74F240 * 74F241 * 74F244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
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74F240 * 74F241 * 74F244 Octal Buffers/Line Drivers with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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